In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device.
Very large scale integration (VLSI) processing dictates that active devices be placed close to one another in a dense fashion. As such, dopant regions, i.e., source regions and drain regions, are implanted at a shallow depth, and are separated from one another by a short channel. The distance between a source region and drain region is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the source region and drain region, the distance between the source region and drain region becomes less than the physical channel length, and is often referred to as the “effective channel length” (Leff).
With increased scaling, as the Leff becomes smaller, a well-known phenomena, known as “short channel effect” (SCE) becomes apparent. Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing subthreshold currents. A problem related to SCE, is the problem of “hot carrier effect” (HCE). HCE is a phenomena by which hot holes and electrons can overcome the potential energy barrier between the silicon and overlying silicon dioxide in order to cause hot carriers to inject into the gate oxide. HCE thereby relates to carrier impact at the substrate topography, whereas SCE relates to carrier impact within the substrate itself.
Additionally, there are significant challenges in designing the electrical characteristics of semiconductor devices, wherein the nature of the inverse relationship between resistance and capacitance makes it difficult to minimize the overall parasitic resistance of the semiconductor device, while also minimizing overall capacitance of the semiconductor device.